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s6b 07 41 128 seg / 12 9 com driver & controller for 4 gray scale stn lcd august 6 . 2000 . ver. 2 . 1 prepared by: hyung-suk, kim highndry@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 2 s6b07 4 1 specification revision history version content date 0 .0 preliminary specification (short form) june 8, 199 9 0 . 1 preliminary specification (full set) july 14, 1 99 9 0 . 2 added temporary pin number (page 5,6) july 15, 1 99 9 0 . 3 removed hpmb, cs2 pins cs1b pin ? csb pin v ol max.: 0. 3 v dd ? 0. 2 v dd , v oh min.: 0. 7 v dd ? 0. 8 v dd (page 59) july 30, 1 99 9 0.4 removed cls, oscck, osc2 pins (page 7,8) read internal status: mf, ds id is added, adc is removed (page 35, 39) reset flag: 0: display o n , 1: display o ff ? 0: display o ff , 1: display o n (page 39) aug. 12, 1 99 9 0.5 changed input pin order, add resetb pin (page 5) added vr, vext pin connection (page 8) vr: when using internal resistors (intrs = " h ") , open this pin vext: when using internal voltage regulator, connect to vdd, vss or open this pin added test pin connection (page 9) test1,test2: connect to ? vdd ? test3,test4,test5: connect to ? vss ? changed osc resistance connection (page8, 23) between osc1 and osc2 ? between osc1 and vdd aug. 30, 1 99 9 0.6 removed test2, test3, test4, test5, test6, test7 pins added coms, coms1 for icon display. added icon control register on/off instruction. sep. 30, 1 99 9 0.7 removed coms, coms1 for icon display. removed icon control register on/off instruction. oct. 4, 1 99 9 1.0 added coms, coms1 for icon display. added icon control register on/off instruction. modified bit settings for partial display command. relaxed v ih and v il specifications. modified interface timing specs . jan. 18, 2000 1.1 added 6800-mode interface description for data latch with csb (page 14) c2 cap value : 0.1 to 0.47uf ? 0.47 to 2.0uf (page 34) added icon mode disabled to the reset default list. (page 36) added description of the column address operation. (page 40) added that display on/off command has priority over entire display on/off and reverse display on/off. (page 44) added n-line inversion command description (page 47) the lower limit of vout, v0 - v4 : +0.3v ? -0.3v (page 60) jan. 24, 2000 1.2 the upper limit of v1 - v4 : v0 ? v0 + 0.3v (page 60) feb. 8, 2000
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 3 s6b07 4 1 specification revision history (continued) version content date 2.0 changed temperature coefficient value (page 1) determined current consumption (page 2, 62) added remarks about oscillator resistor (page 61, 63) changed parallel interface timing (page 17, 64, 65) jun. 26, 2000 2.1 removed wrong description about display data ram. (page 1) aug. 6, 2000
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 4 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 features ................................ ................................ ................................ ................................ ......................... 1 block diagram ................................ ................................ ................................ ................................ .............. 3 pad configuration ................................ ................................ ................................ ................................ ....... 4 pad center coordinates ................................ ................................ ................................ ................................ .... 6 pin description ................................ ................................ ................................ ................................ .............. 6 power supply ................................ ................................ ................................ ................................ ......... 9 lcd driver supply ................................ ................................ ................................ ................................ . 9 system control ................................ ................................ ................................ ................................ ... 10 microprocessor interface ................................ ................................ ................................ ............ 11 lcd driver outputs ................................ ................................ ................................ ............................ 13 functional description ................................ ................................ ................................ ........................... 14 microprocessor interface ................................ ................................ ................................ ............ 14 display data ram (ddram) ................................ ................................ ................................ ................. 18 lcd display circuits ................................ ................................ ................................ ........................... 21 lcd driver circuit ................................ ................................ ................................ ............................... 26 power supply circuits ................................ ................................ ................................ ...................... 29 referece circuit examples ................................ ................................ ................................ ............. 34 reset circuit ................................ ................................ ................................ ................................ ........ 36 instruction description ................................ ................................ ................................ .......................... 37 specifications ................................ ................................ ................................ ................................ ............. 60 absolute maximum ratings ................................ ................................ ................................ .............. 60 dc characteristics ................................ ................................ ................................ ............................ 61 ac characteristics ................................ ................................ ................................ ............................ 64 reference applications ................................ ................................ ................................ .......................... 68 microprocessor interface ................................ ................................ ................................ ............ 68 connections between s6b07 4 1 and lcd panel ................................ ................................ ........... 70
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 1 introduction the S6B0741 is a driver & controller lsi for 4-level gray scale graphic dot-matrix liquid crystal display systems. it contains 12 8 segment and 12 9 common driver circuits. this chip is connected directly to a microprocessor, accepts serial peripheral interface (spi) or 8-bit parallel display data and stores in an on-chip display data ram of 12 8 x 12 9 x 2 bits . it performs display data ram read/write operation with no external operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features 4-level ( w hite, l ight g ray, d ark g ray, b lack) g ray s cale d isplay with pwm and frc m ethod s ddram data [2n: 2n+1] 00 01 10 11 gray scale white light gray dark gray dark (accessible c olumn a ddress, n = 0, 1, 2, ? ? , 125, 126, 127) driver output circuits - 128 segment outputs / 129 common outputs applicable duty ratios d uty ratio applicable lcd bias maximum display area 1/16 ~ 1/12 8 (icon disabled) 1/17 ~ 1/12 9 (icon enabled) 1/5 to 1/12 12 9 12 8 - various partial display - partial window moving & data scrolling on-chip display data ram - capacity: 12 9 12 8 2 = 33,024 bits microprocessor interface - 8-bit parallel bi-directio nal interface with 6800-series or 8080-series - spi ( serial p eripheral interface ) available (only write operation) on-chip l ow p ower analog circuit - on-chip oscillator circuit - voltage converter ( x3, x4, 5 or x6 ) - voltage regulator ( t emperature coefficient : -0.125%/ c, or external input ) - on-chip e lectronic contrast control function (64 steps) - voltage follower (lcd bias : 1/5 to 1/12) operating voltage range - supply voltage (v dd ): 1.8 to 3.3 v - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 1 5 .0 v
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 2 low power consumption - 300 m a max. (o peration ) - 2 m a m ax. ( sleep mo de) package type - slim chip for tcp
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 3 block diagram frc/pwm function circuit vdd v0 v1 v2 v3 v4 vss v0 vr intrs vext ref vout c1 - c1 + c2 - c2 + c3 + c 4+ c 5+ vcl v / c circuit v / r circuit v / f circuit mpu interface (parallel & serial) instruction decoder bus holder column address circuit display latch circuit common output controller circuit db0 db1 db2 db3 db4 db5 db6(sclk) db7(s id ) rw_wr e_rd rs csb ps0 ps1 resetb coms1 com127 com126 : com1 com0 coms seg127 seg126 seg125 : seg2 seg1 seg0 oscillator / display timing control 128 segment driver circuits line address circuit page address circuit display data ram 129 x 128 x 2 = 33 , 024 bits i/o buffer status register instruction register osc1 129 common driver circuits internal power supply test1 figure 1 . block diagram
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 4 pad configuration ? .. ? .. ....................... .. ............ . x y (0,0) S6B0741 pad 374 375 144 180 181 1 143 411 figure 2 . s6b07 4 1 chip configuration table 1 . s6b07 4 1 pad dimensions item pad no. size unit x y chip size - 1 0 5 8 0 2 5 2 0 - pad pitch 1 ~ 1 4 3 7 0 1 4 4 ~ 1 7 8 1 8 3 ~ 3 7 2 3 7 7 ~ 4 1 1 5 2 1 7 9 ~ 1 8 2 3 7 3 ~ 3 7 6 8 0 bumped pad size 1 ~ 1 4 3 4 2 9 2 1 4 5 ~ 1 7 8 3 7 7 ~ 4 1 0 7 0 3 4 1 8 3 ~ 3 7 2 3 4 7 0 1 4 4 1 7 9 ~ 1 8 0 3 7 5 ~ 3 7 6 4 1 1 7 0 6 2 1 8 1 ~ 1 8 2 3 7 3 ~ 3 7 4 6 2 7 0 bumped pad height all pad 1 4 ( typ)
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 5 cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (+ 4527 , +624.5 ) 30 m m 30 m m 30 m m ( -4690 , -515 ) 30 m m 30 m m 30 m m 60 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (- 4607 , +704.5 ) (+4 770, -580 )
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 6 pad center coordinates table 2. p ad center coordinates [unit: m m] no. name x y no. name x y no. name x y no. name x y 1 dummy -4970 -1145 51 dummy -1470 -1145 101 c3+ 2030 -1145 151 com57 5166 -586 2 dummy -4900 -1145 52 dummy -1400 -1145 102 c3+ 2100 -1145 152 com56 5166 -534 3 dummy -4830 -1145 53 dummy -1330 -1145 103 c1- 2170 -1145 153 com55 5166 -482 4 dummy -4760 -1145 54 dummy -1260 -1145 104 c1- 2240 -1145 154 com54 5166 -430 5 dummy -4690 -1145 55 dummy -1190 -1145 105 c1+ 2310 -1145 155 com53 5166 -378 6 dummy -4620 -1145 56 dummy -1120 -1145 106 c1+ 2380 -1145 156 com52 5166 -326 7 dummy -4550 -1145 57 dummy -1050 -1145 107 c2+ 2450 -1145 157 com51 5166 -274 8 dummy -4480 -1145 58 dummy -980 -1145 108 c2+ 2520 -1145 158 com50 5166 -222 9 dummy -4410 -1145 59 vdd -910 -1145 109 c2- 2590 -1145 159 com49 5166 -170 10 dummy -4340 -1145 60 test1 -840 -1145 110 c2- 2660 -1145 160 com48 5166 -118 11 dummy -4270 -1145 61 vss -770 -1145 111 c4+ 2730 -1145 161 com47 5166 -66 12 dummy -4200 -1145 62 ps0 -700 -1145 112 c4+ 2800 -1145 162 com46 5166 -14 13 dummy -4130 -1145 63 vdd -630 -1145 113 vdd 2870 -1145 163 com45 5166 38 14 dummy -4060 -1145 64 ps1 -560 -1145 114 vdd 2940 -1145 164 com44 5166 90 15 dummy -3990 -1145 65 vss -490 -1145 115 ref 3010 -1145 165 com43 5166 142 16 dummy -3920 -1145 66 csb -420 -1145 116 vss 3080 -1145 166 com42 5166 194 17 dummy -3850 -1145 67 resetb -350 -1145 117 vext 3150 -1145 167 com41 5166 246 18 dummy -3780 -1145 68 vdd -280 -1145 118 vdd 3220 -1145 168 com40 5166 298 19 dummy -3710 -1145 69 rs -210 -1145 119 intrs 3290 -1145 169 com39 5166 350 20 dummy -3640 -1145 70 rw_wr -140 -1145 120 vss 3360 -1145 170 com38 5166 402 21 dummy -3570 -1145 71 vss -70 -1145 121 vss 3430 -1145 171 com37 5166 454 22 dummy -3500 -1145 72 e_rd 0 -1145 122 v4 3500 -1145 172 com36 5166 506 23 dummy -3430 -1145 73 vdd 70 -1145 123 v4 3570 -1145 173 com35 5166 558 24 dummy -3360 -1145 74 db0 140 -1145 124 v3 3640 -1145 174 com34 5166 610 25 dummy -3290 -1145 75 db1 210 -1145 125 v3 3710 -1145 175 com33 5166 662 26 dummy -3220 -1145 76 db2 280 -1145 126 v2 3780 -1145 176 com32 5166 714 27 dummy -3150 -1145 77 db3 350 -1145 127 v2 3850 -1145 177 com31 5166 766 28 dummy -3080 -1145 78 db4 420 -1145 128 v1 3920 -1145 178 com30 5166 818 29 dummy -3010 -1145 79 db5 490 -1145 129 v1 3990 -1145 179 dummy 5166 884 30 dummy -2940 -1145 80 db6 560 -1145 130 v0 4060 -1145 180 dummy 5166 964 31 dummy -2870 -1145 81 db7 630 -1145 131 v0 4130 -1145 181 dummy 5060 1136 32 dummy -2800 -1145 82 vdd 700 -1145 132 vr 4200 -1145 182 dummy 4980 1136 33 dummy -2730 -1145 83 vdd 770 -1145 133 vr 4270 -1145 183 com29 4914 1136 34 dummy -2660 -1145 84 vdd 840 -1145 134 vss 4340 -1145 184 com28 4862 1136 35 dummy -2590 -1145 85 vdd 910 -1145 135 vss 4410 -1145 185 com27 4810 1136 36 dummy -2520 -1145 86 vdd 980 -1145 136 vdd 4480 -1145 186 com26 4758 1136 37 dummy -2450 -1145 87 vdd 1050 -1145 137 osc1 4550 -1145 187 com25 4706 1136 38 dummy -2380 -1145 88 vci 1120 -1145 138 dummy 4620 -1145 188 com24 4654 1136 39 dummy -2310 -1145 89 vci 1190 -1145 139 dummy 4690 -1145 189 com23 4602 1136 40 dummy -2240 -1145 90 vss 1260 -1145 140 dummy 4760 -1145 190 com22 4550 1136 41 dummy -2170 -1145 91 vss 1330 -1145 141 dummy 4830 -1145 191 com21 4498 1136 42 dummy -2100 -1145 92 vss 1400 -1145 142 dummy 4900 -1145 192 com20 4446 1136 43 dummy -2030 -1145 93 vss 1470 -1145 143 dummy 4970 -1145 193 com19 4394 1136 44 dummy -1960 -1145 94 vss 1540 -1145 144 dummy 5166 -964 194 com18 4342 1136 45 dummy -1890 -1145 95 vss 1610 -1145 145 com63 5166 -898 195 com17 4290 1136 46 dummy -1820 -1145 96 vss 1680 -1145 146 com62 5166 -846 196 com16 4238 1136 47 dummy -1750 -1145 97 vout 1750 -1145 147 com61 5166 -794 197 com15 4186 1136 48 dummy -1680 -1145 98 vout 1820 -1145 148 com60 5166 -742 198 com14 4134 1136 49 dummy -1610 -1145 99 c5+ 1890 -1145 149 com59 5166 -690 199 com13 4082 1136 50 dummy -1540 -1145 100 c5+ 1960 -1145 150 com58 5166 -638 200 com12 4030 1136
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 7 table 2 . pad center coordinates (continued) [unit: m m ] no. name x y no. name x y no. name x y no. name x y 201 com11 3978 1136 251 seg37 1378 1136 301 seg87 -1222 1136 351 com73 -3822 1136 202 com10 3926 1136 252 seg38 1326 1136 302 seg88 -1274 1136 352 com74 -3874 1136 203 com9 3874 1136 253 seg39 1274 1136 303 seg89 -1326 1136 353 com75 -3926 1136 204 com8 3822 1136 254 seg40 1222 1136 304 seg90 -1378 1136 354 com76 -3978 1136 205 com7 3770 1136 255 seg41 1170 1136 305 seg91 -1430 1136 355 com77 -4030 1136 206 com6 3718 1136 256 seg42 1118 1136 306 seg92 -1482 1136 356 com78 -4082 1136 207 com5 3666 1136 257 seg43 1066 1136 307 seg93 -1534 1136 357 com79 -4134 1136 208 com4 3614 1136 258 seg44 1014 1136 308 seg94 -1586 1136 358 com80 -4186 1136 209 com3 3562 1136 259 seg45 962 1136 309 seg95 -1638 1136 359 com81 -4238 1136 210 com2 3510 1136 260 seg46 910 1136 310 seg96 -1690 1136 360 com82 -4290 1136 211 com1 3458 1136 261 seg47 858 1136 311 seg97 -1742 1136 361 com83 -4342 1136 212 com0 3406 1136 262 seg48 806 1136 312 seg98 -1794 1136 362 com84 -4394 1136 213 coms 3354 1136 263 seg49 754 1136 313 seg99 -1846 1136 363 com85 -4446 1136 214 seg0 3302 1136 264 seg50 702 1136 314 seg100 -1898 1136 364 com86 -4498 1136 215 seg1 3250 1136 265 seg51 650 1136 315 seg101 -1950 1136 365 com87 -4550 1136 216 seg2 3198 1136 266 seg52 598 1136 316 seg102 -2002 1136 366 com88 -4602 1136 217 seg3 3146 1136 267 seg53 546 1136 317 seg103 -2054 1136 367 com89 -4654 1136 218 seg4 3094 1136 268 seg54 494 1136 318 seg104 -2106 1136 368 com90 -4706 1136 219 seg5 3042 1136 269 seg55 442 1136 319 seg105 -2158 1136 369 com91 -4758 1136 220 seg6 2990 1136 270 seg56 390 1136 320 seg106 -2210 1136 370 com92 -4810 1136 221 seg7 2938 1136 271 seg57 338 1136 321 seg107 -2262 1136 371 com93 -4862 1136 222 seg8 2886 1136 272 seg58 286 1136 322 seg108 -2314 1136 372 com94 -4914 1136 223 seg9 2834 1136 273 seg59 234 1136 323 seg109 -2366 1136 373 dummy -4980 1136 224 seg10 2782 1136 274 seg60 182 1136 324 seg110 -2418 1136 374 dummy -5060 1136 225 seg11 2730 1136 275 seg61 130 1136 325 seg111 -2470 1136 375 dummy -5166 964 226 seg12 2678 1136 276 seg62 78 1136 326 seg112 -2522 1136 376 dummy -5166 884 227 seg13 2626 1136 277 seg63 26 1136 327 seg113 -2574 1136 377 com95 -5166 818 228 seg14 2574 1136 278 seg64 -26 1136 328 seg114 -2626 1136 378 com96 -5166 766 229 seg15 2522 1136 279 seg65 -78 1136 329 seg115 -2678 1136 379 com97 -5166 714 230 seg16 2470 1136 280 seg66 -130 1136 330 seg116 -2730 1136 380 com98 -5166 662 231 seg17 2418 1136 281 seg67 -182 1136 331 seg117 -2782 1136 381 com99 -5166 610 232 seg18 2366 1136 282 seg68 -234 1136 332 seg118 -2834 1136 382 com100 -5166 558 233 seg19 2314 1136 283 seg69 -286 1136 333 seg119 -2886 1136 383 com101 -5166 506 234 seg20 2262 1136 284 seg70 -338 1136 334 seg120 -2938 1136 384 com102 -5166 454 235 seg21 2210 1136 285 seg71 -390 1136 335 seg121 -2990 1136 385 com103 -5166 402 236 seg22 2158 1136 286 seg72 -442 1136 336 seg122 -3042 1136 386 com104 -5166 350 237 seg23 2106 1136 287 seg73 -494 1136 337 seg123 -3094 1136 387 com105 -5166 298 238 seg24 2054 1136 288 seg74 -546 1136 338 seg124 -3146 1136 388 com106 -5166 246 239 seg25 2002 1136 289 seg75 -598 1136 339 seg125 -3198 1136 389 com107 -5166 194 240 seg26 1950 1136 290 seg76 -650 1136 340 seg126 -3250 1136 390 com108 -5166 142 241 seg27 1898 1136 291 seg77 -702 1136 341 seg127 -3302 1136 391 com109 -5166 90 242 seg28 1846 1136 292 seg78 -754 1136 342 com64 -3354 1136 392 com110 -5166 38 243 seg29 1794 1136 293 seg79 -806 1136 343 com65 -3406 1136 393 com111 -5166 -14 244 seg30 1742 1136 294 seg80 -858 1136 344 com66 -3458 1136 394 com112 -5166 -66 245 seg31 1690 1136 295 seg81 -910 1136 345 com67 -3510 1136 395 com113 -5166 -118 246 seg32 1638 1136 296 seg82 -962 1136 346 com68 -3562 1136 396 com114 -5166 -170 247 seg33 1586 1136 297 seg83 -1014 1136 347 com69 -3614 1136 397 com115 -5166 -222 248 seg34 1534 1136 298 seg84 -1066 1136 348 com70 -3666 1136 398 com116 -5166 -274 249 seg35 1482 1136 299 seg85 -1118 1136 349 com71 -3718 1136 399 com117 -5166 -326 250 seg36 1430 1136 300 seg86 -1170 1136 350 com72 -3770 1136 400 com118 -5166 -378
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 8 table 2 . pad center coordinates (continued) [unit: m m ] no. name x y no. name x y no. name x y no. name x y 401 com119 -5166 -430 402 com120 -5166 -482 403 com121 -5166 -534 404 com122 -5166 -586 405 com123 -5166 -638 406 com124 -5166 -690 407 com125 -5166 -742 408 com126 -5166 -794 409 com127 -5166 -846 410 coms1 -5166 -898 411 dummy -5166 -964
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 9 pin description power supply table 3. power supply pin description name i/o description vdd supply power supply v ss supply ground lcd driver supply voltages the voltage determined by lcd pixel is impedance - converted by an operational amplifier for application. voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd bias. lcd bias v1 v2 v3 v4 1/n bias (n-1) / n x v0 (n-2) / n x v0 (2/n) x v0 ( 1/ n) x v0 v0 v1 v2 v3 v4 i/o note: n = 5 to 1 2 lcd driver supply table 4. lcd driver supply pin description name i/o description c1- o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2- o capacitor 2 negative connection pin for voltage converter c2+ o capacitor 2 positive connection pin for voltage converter c 3 + o capacitor 3 positive connection pin for voltage converter c 4 + o capacitor 4 positive connection pin for voltage converter c 5 + o capacitor 5 positive connection pin for voltage converter vout i/o voltage converter input / output pin vcl i voltage converter input voltage pin vr i v0 voltage adjustment pin it is valid only when on-chip resistors are not used (intrs = "l") when using internal resistors (intrs = " h ") , open this pin ref i selects the external vref voltage via the vext pin - ref = ? h ? : u sing the internal vref - ref = ? l ? : u sing the external vref v ext i externally input reference voltage (vref) for the internal voltage regulator it is valid only when ref is "l" when using internal voltage regulator, connect to vdd, vss or open this pin osc1 i when using internal clock oscillator, connect a resistor between osc1 and vdd.
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 10 system control table 5. system c ontrol pin description name i/o description intrs i internal resistor select pin this pin selects the resistors for adjusting v0 voltage level - intrs = "h": use the internal resistors. - intrs = "l": use the external resistors vr pin and external resistive divider control v0 voltage test1 o test pins don ? t use th is pin. - test1: open this pin.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 11 microprocessor interface table 6. microprocessor i nterface pin description name i/o description reset b i reset input pin when reset b is ? l ? , initialization is executed. parallel / serial data input select input ps 0 interface mode data / instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs or none sid (db7) write only sclk (db6) ps 0 i *note: in serial mode , it is impossible to read data from the on-chip ram. and db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either ? h ? or ? l ? . ps1 i microprocessor interface select input pin - ps0 = ? h ? , ps1 = "h": 6800-series parallel mpu interface - ps0 = ? h ? , ps1 = "l": 8080-series parallel mpu interface - ps0 = ? l ? , ps1 = "h": 4 p in-spi mpu interface - ps0 = ? l ? , ps1 = "l": 3 p in-spi mpu interface csb i chip select input pins data/instruction i/o is enabled only when csb is "l". when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin c68 mpu type rw_wr description h 6800-series rw read / write control input pin - rw = ? h ? : r ead - rw = ? l ? : w rite l 8080-series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw _wr i
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 12 table 7. microprocessor i nterface pin description (continued) name i/o description read / write execution control pin ps1 mpu type e_rd description h 6800-series e read / write control input pin - rw = ? h ? : when e is ? h ? , db0 to db7 are in an output status. - rw = ? l ? : the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is ? l ? , db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps 0 = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 13 lcd driver outputs table 8. lcd d river o utput pin description name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m (internal) normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg 0 to seg 127 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (internal) common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com 0 t o com 127 o coms (coms1) o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. note: dummy ? these pins should be opened (floated).
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 14 functional description microprocessor interface chip select input there is csb pin for chip selection. the s6b07 41 can interface with an mpu when csb is "l". when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface s6b07 4 1 has four types of interface with an mpu, which are two serial and two parallel interface s . this parallel or serial interface is determined by ps pin as shown in table 9 . table 9 . parallel / serial interface mode type ps1 csb ps 0 interface mode h 6800-series mpu mode parallel l csb h 8080-series mpu mode h 4- p in spi mode serial l csb l 3- p in spi mode parallel interface (ps 0 = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by ps1 as shown in table 10 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 11 . table 10 . microprocessor selection for parallel interface ps1 csb rs e_rd rw_wr db0 to db7 mpu bus h csb rs e rw db0 to db7 6800-series l csb rs /rd /wr db0 to db7 8080-series table 11 . parallel data transfer common 6800-series 8080-series rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (i ns truction) note: when e_rd pin is always pulled high for 6800-series interface, it can be used csb for enable signal. in this case, interface data is latched at the rising edge of csb and t he type of data transfer is determined by signals at rs, rw_wr as in case of 6800-series mode .
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 15 serial interface (ps 0 = "l") when the s6b07 4 1 is active (csb= ? l ? ) , serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. the display data/command indication may be controlled either via software or the register select(rs) pin, based on the setting of ps1. when the rs pin is used (ps1 = ? h ? ), data is display data when rs is high, and command data when rs is low. when rs is not used (ps1 = ? l ? ), the lcd driver will receive command from mcu by default. if messages on the data pin are data rather than command, mcu should send data direction command(11101000) to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are send, the following messages will be data rather than command. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. and the ddram column address pointer will be increased by one automatically. the next bytes after the display data string is handled as command data. serial mode ps0 ps1 csb rs 4-pin spi mode l h csb used 3-pin spi mode l l csb not used 4- p in spi mode (ps 0 = "l" , ps1 = " h ") cs b sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . 4 -p in spi timing (rs is used)
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 16 3- p in spi mode (ps 0 = "l" , ps1 = " l ") to write data to the ddram, send data direction command in 3- p in spi mode. data is latched at the rising edge of s clk. and the ddram column address pointer will be increased by one automatically. (1) set page and column address. set page address : 1 0 1 1 p3 p2 p1 p0 set column address msb : 0 0 0 1 0 y6 y5 y4 set column address lsb : 0 0 0 0 y3 y2 y1 y0 (2) set ddc(data direction command) and no. of data bytes. set data direction command ( for spi mode only): 1 1 1 0 1 0 0 0 set no. of data bytes : d7 d6 d5 d4 d3 d2 d1 d0 (3) this figure is example for 104 data bytes to be transfered . (1) ( s clk csb 829 830 831 0 0 1 7 8 15 23 sid msb data in page lsb ddc no. of data 3 byte (1) 2 byte (2) 104 byte 0 figure 4 . 3 -p in spi timing (rs is not used) this command is used in 3- p in spi mode only. it will be two continuous commands, the first byte control s the data direction and inform s the lcd driver the second byte will be number of data bytes will be write. after these two commands sending out, the following messages will be data. if data is stopped in transmitting, i t i s not valid data. new d ata will be transferred serially with most significant bit first. note: in spite of transmission of d ata, if csb will be disable, state terminates abnormally. next state is initialized. busy flag the b usy f lag indicates whether the s6b07 41 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 17 data transfer the s6b07 4 1 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 5 . and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 6 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 5 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 d(n+ 2 ) figure 6 . read timing
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 18 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 129 -row (17 page by 8 bits) by 128 -column addressable array. each pixel can be selected when the page and column addresses are specified. the 129 rows are divided into 16 pages of 8 lines and the 17th page with a single line (db0 only) . data is read from or written to the 8 lines of each page directly through db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines . t he microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. page address circuit this circuit is for providing a page address to d isplay d ata ram shown in figure 8 . it incorporates 4-bit page address register changed by only the ? set page ? instruction. page address 16 is a special ram area for the icons and display data db0 is only valid. line address circuit this circuit assigns ddram a line address corresponding to the first line (com 0 ) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 8 . it incorporates 7 -bit line address register changed by only the initial display line instruction and 7 -bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the line address for transferring the 128 -bit ram data to the display data latch circuit. when icon is enabled by setting icon control register, display data of icons are not scrolled because the mpu can not access line address of icons.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 19 column address circuit column address circuit has a 8 -bit preset counter that provides column address to the d isplay d ata ram as shown in figure 8 . when set column address msb / lsb instruction is issued, 7 -bit [y 7 :y 1 ] are set and lowest bit, y0 is set to ? 0 ? . s ince this address is increased by 1 each a r ead or w rite d ata instruction, microprocessor can access the display data continuously. however, the counter is not incre as ed and locked if a non-existing address above 7e h. it is unlocked if a column address is set again by s et c olumn address msb / lsb instruction. and t he column address counter is independent of page address register. adc s elect instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc s elect instruction. refer to the following figure 7 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 124 seg 125 seg 126 seg 127 column address [y 7 :y 1 ] 00h 01h 02h 03h ... ... 7c h 7d h 7e h 7f h internal c olumn address [y7:y0] 00 hex 01 hex 02 hex 03 hex 04 hex 05 hex 06 hex 07 hex ... ... f8 hex f9 hex fa hex fb hex fc hex fd hex fe hex ff hex display data (adc = 0) 1 1 1 0 0 0 0 1 ... ... 1 0 1 1 0 0 0 1 lcd panel display ... ... display data (adc = 1 ) 0 1 0 0 1 1 1 0 ... ... 0 1 0 0 1 0 1 1 lcd panel display ... ... figure 7 . the relationship b etween t he column address a nd the segment outputs segment control circuit this circuit controls the display data by the d isplay on / off, r everse d isplay on / off and e ntire d isplay on / off instructions without changing the data in the display data ram.
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 20 line address com output page address data initial start line address = 08h 02 page 0 db0 db1 db2 db3 db4 db5 db6 db7 00h 01h 02h 03h 04h 05h 06h 07h page 1 db0 db1 db2 db3 db4 db5 db6 db7 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh page 2 db0 db1 db2 db3 db4 db5 db6 db7 page 3 db0 db1 db2 db3 db4 db5 db6 db7 page 12 db0 db1 db2 db3 db4 db5 db6 db7 page 13 db0 db1 db2 db3 db4 db5 db6 db7 page 14 db0 db1 db2 db3 db4 db5 db6 db7 page 15 db0 db1 db2 db3 db4 db5 db6 db7 03 01 04 05 - - - - - - - - 7c 7d 7a 7b 7e 7f 02 03 00 01 04 05 - - - - - - - - 7c 7d 7a 7b 7e 7f adc=0 adc=1 column address [y7:y1] 00 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com96 com97 com98 com99 com100 com101 com102 com103 com104 com105 com106 com107 com108 com109 com110 com111 com112 com113 com114 com115 com116 com117 com118 com119 com120 com121 com122 com123 com124 com125 com126 com127 lcd segment output - - - - - - - - seg0 seg1 seg2 seg3 seg4 seg5 seg122 seg123 seg124 seg125 seg126 seg127 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh 60h 61h 62h 63h 64h 65h 66h 67h 1/129 duty 1/121 duty start = 08h end = 07h 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 db3 db0 db1 db2 db4 0 0 0 0 1 db0 page 16 (*) 80h coms (*) when icon control register is set to "1", page address is set to "16". and user can write data for displaying icons. figure 8 . display data ram map
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 21 lcd display circuits frc (frame rate control) and pwm (pulse width modulation) function circuit the S6B0741 incorporates an frc function and a pwm function circuit to display a 4-level gray scale. the frc function and pwm utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. the S6B0741 provides four 4-bit palette-registers to assign the desired gray level. th e se register s are set by the instructions and the resetb. - gray s cale t able of 4 frc (frame rate control) gray s cale l evel msb (db7 to db4) lsb (db3 to db0) 2nd fr (fr2) 1st fr (fr1) white 4th fr (fr4) 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) light g ray 4th fr (fr4) 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) dark g ray 4th fr (fr4) 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) black 4th fr (fr4) 3rd fr (fr3) - gray s cale t able of 3 frc (frame rate control) gray s cale l evel msb (db7 to db4) lsb (db3 to db0) 2nd fr (fr2) 1st fr (fr1) white 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) light g ray 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) dark g ray 3rd fr (fr3) 2nd fr (fr2) 1st fr (fr1) black 3rd fr (fr3)
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 22 - gray s cale t able of 15 pwm (pulse width modulation) dec hex 4- b its pwm (on width) note 0 00 0000 0 (0/15) brighter 1 01 0001 1/15 2 02 0010 2/15 3 03 0011 3/15 4 04 0100 4/15 5 05 0101 5/15 6 06 0110 6/15 7 07 0111 7/15 8 08 1000 8/15 9 09 1001 9/15 10 0a 1010 10/15 11 0b 1011 11/15 12 0c 1100 12/ 1 5 13 0d 1101 13/15 14 0e 1110 14/15 15 0f 1111 1 (15/15) darker - gray s cale t able of 12 pwm (pulse width modulation) dec hex 4- b its pwm (on width) note 0 00 0000 0 (0/12) brighter 1 01 0001 1/12 2 02 0010 2/12 3 03 0011 3/12 4 04 0100 4/12 5 05 0101 5/12 6 06 0110 6/12 7 07 0111 7/12 8 08 1000 8/12 9 09 1001 9/12 10 0a 1010 10/12 11 0b 1011 11/12 12 0c 1100 1 (12/12) darker 13 0d 1101 0/12 14 0e 1110 0/12 15 0f 1111 0/12 this area is selected to off level (0/12 level)
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 23 - gray s cale t able of 9 pwm (pulse width modulation) dec hex 4- b its pwm (on width) note 0 00 0000 0 (0/9) brighter 1 01 0001 1/9 2 02 0010 2/9 3 03 0011 3/9 4 04 0100 4/9 5 05 0101 5/9 6 06 0110 6/9 7 07 0111 7/9 8 08 1000 8/9 9 09 1001 1 (9/9) darker 10 0a 1010 0/9 11 0b 1011 0/9 12 0c 1100 0/9 13 0d 1101 0/9 14 0e 1110 0/9 15 0f 1111 0/9 this area is selected to off level (0/9 level)
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 24 oscillator this is on-chip o scillator with external resistor. i ts frequency is controlled by external re s istor between osc1 and vdd. this o scillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl (internal) , generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 1 28 -bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line signal changes the m by setting internal instruction. driving waveform and internal timing signal are shown in figure 9. fr(internal) m(internal) 127 128 1 2 3 4 5 6 7 8 9 10 11 12 121 122 123 124 125 126 127 128 1 2 3 4 5 6 cl(internal) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 9 . 2-frame ac driving waveform (duty ratio = 1/ 128 )
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 25 fr(internal) m(internal) 127 128 1 2 3 4 5 6 7 8 9 10 11 12 119 120 121 122 123 124 125 126 127 128 1 2 3 4 cl(internal) com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 10 . n-line inversion driving waveform (n = 5, duty ratio = 1/ 128 )
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 26 lcd driver circuit this driver circuit is configured by 129-c hannel common drivers and 1 28 -channel segment drivers. this lcd panel driver voltage depends on the combination of display data and m signal. com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com1 0 com1 1 com1 2 com1 3 com1 4 com 15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg 2 seg 1 seg 0 com 2 com 0 com 1 m v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v0 v1 v2 v3 v4 v ss v dd v ss figure 11 . segment and common timing
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 27 partial display on lcd the s6b07 41 realizes the partial display function on lcd with low-duty driving for saving power consumption and showing the various display duty. to show the various display duty on lcd, lcd driving duty and bias are programmable via the instruction. and, built-in power supply circuits are controlled by the instruction for adjusting the lcd driving voltages -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 12 . reference example for partial display -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 13 . partial display (partial display duty = 16 , initial com0 = 0)
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 28 -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 14 . moving display (partial display duty = 16 , initial com0 = 8)
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 29 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are controlled by p ower c ontrol instruction. for details, refers to "instruction description". table 12 shows the referenced combinations in using p ower s upply circuits. table 12 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 o n o n o n open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 o ff o n on external input open open only the voltage follower circuits are used 0 0 1 o ff o ff o n open external input open only the external power supply circuits are used 0 0 0 o ff o ff o ff open external input external input
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 30 voltage converter circuits these circuits boost up the electric potential between vci and vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ? set dc-dc step-up ? instruction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + vout = 3 x vci c1 - + c1 - + - vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - vout = 4 x vci figure 15 . three times boosting circuit figure 16 . four times boosting circuit vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - c1 - + - c1 - + c1 - + vout = 5 x vci vout = 6 x vci c1 - + - figure 17 . five times boosting circuit figure 18 . six times boosting circuit
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 31 voltage regulator circuits the function of the internal v oltage r egulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational-amplifier circuits shown in figure 19 , it is necessary to be applied internally or externally. for the eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta= 25 c is shown in table 13 . rb v0 = (1 + ???? ) x v ev [v] ------ ( eq. 1) ra (63 - a ) v ev = (1 - ?????? ) x v ref [v] ------ ( eq. 2) 2 1 0 table 13 . v ref voltage at ta = 25 c ref temp. coefficient v ref [ v ] 1 - 0.125 % / c 2. 1 0 external input vext v ev gnd ra rb vss vr v0 vout + - figure 19 . internal voltage regulator circuit
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 32 in case of using internal resistors, ra and rb (intrs = "h ? ) when intrs pin is " h " , resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 14 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 2. 3 3. 0 3 . 7 4 . 4 5 . 1 5 . 8 6 . 5 7 . 2 figure 20 shows v0 voltage measured by adjusting internal regulator register ratio ( rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 electronic volume register (0 to 63) v0 voltage [v] (1, 1, 1) 63 63 (1, 1, 0) (1, 0, 1) (1, 0 ,0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) figure 20 . electronic volume level (temp. coefficient = - 0.125 % / c)
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 33 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is " l " , it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 ua from eq. 1 rb 10 = (1 + ??? ) x v ev [v] ------ ( eq. 3) ra from eq. 1 (63 - 32) v ev = (1 - ?????? ) x 2. 1 = 1. 7 9 [v] ------ ( eq. 4) 2 1 0 from requirement 3. 10 ????? = 1 [ ua] ------ ( eq. 5) ra + rb from equations eq. 3, 4 and 5 ra = 1. 7 9 [m w ] rb = 8. 2 1 [m w ] table 15 shows the range of v0 depending on the above requirements. table 15. the r ange of v0 electronic volume level 0 ....... 32 ....... 63 v0 8. 21 ....... 10.00 ....... 11. 7 3 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and those output impedance are converted by the v oltage f ollower for increasing drive capability. table 16 shows the relationship between v1 to v4 level and each duty ratio. table 16. the relationship between v1 to v4 level and each duty ratio lcd bias v1 v2 v3 v4 remarks 1/ n ( n -1)/ n x v0 ( n - 2 )/ n x v0 2/ n x v0 1/ n x v0 n = 5 to 1 2
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 34 reference circuit examples [c1 = 1.0 to 4.7 [ m f], c2 = 0.47 to 2.0 [ m f]] when using internal regulator resistors when not using internal regulator resistors v ss c1 c1 c1 c1 c1 c1 + + + + + v dd intrs vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c1 c1 c1 c1 c1 c1 + + + + + vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss r b ra c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 intrs figure 21. when using a ll lcd power circuits (6-time v/c: o n , v/r: o n , v/f: o n ) [c2 = 0.47 to 2.0 [ m f]] when using internal regulator resistors when not using internal regulator resistors intrs v ss ra rb v ss v dd intrs v ss external power supply external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 c2 - + c2 - + c2 - + c2 - + c2 - + vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 figure 22. when using s ome lcd power circuits (v/c: o ff , v/r: o n , v/f: o n )
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 35 [c2 = 0.47 to 2.0 [ m f]] v dd intrs v ss external power supply c2 - + c2 - + c2 - + c2 - + c2 - + vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 figure 23. when using s ome lcd power circuits (v/c: o ff , v/r: o ff , v/f: o n ) [c2 = 0.47 to 2.0 [ m f]] v dd intrs v ss external power supply vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 figure 24. when not using a ny internal lcd power supply circuits (v/c: o ff , v/r: o ff , v/f: o ff )
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 36 reset circuit setting resetb to ? l ? or reset instruction can initialize internal function. when resetb becomes ? l ? , following procedure is occurred. page address: 0 column address: 0 r ead -m odify- write : off display on / off: off initial display line: 0 (first) initial com0 register: 0 (com0) partial display duty ratio: 1/ 128 reverse display on / off: off (normal) n -line inversion register: 0 (disable) entire display on/off: off icon control register on/off: off (icon disable) power control register (vc, vr, vf) = ( 0 , 0, 0) dc-dc converter circuit = (0, 0) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) contrast level: 32 lcd bias ratio: 1/ 12 com scan direction: 0 adc select: 0 oscillator: off power save mode: release display data length register: 0 (for spi mode) white mode set: off white palette register (wg3, wg2, wg1, wg0) = (0, 0, 0, 0) light gray mode set: off light gray palette register (lg3, lg2, lg1, lg0) = (0, 0, 0, 0) dark gray mode set: off dark gray palette register (dg3, dg2, dg1, dg0) = (1, 1, 1, 1) black mode set: off black palette register (bg3, bg2, bg1, bg0) = (1, 1, 1, 1) frc, pwm mode: 4frc, 9pwm when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 r ead -m odify- write : off initial display line: 0 (first) regulator resistor select register: (r2, r1, r0) = ( 0, 0 , 0) contrast level: 32 display data length register: 0 (for spi mode) white mode set: off white palette register (wg3, wg2, wg1, wg0) = (0, 0, 0, 0) light gray mode set: off light gray palette register (lg3, lg2, lg1, lg0) = (0, 0, 0, 0) dark gray mode set: off dark gray palette register (dg3, dg2, dg1, dg0) = (1, 1, 1, 1) black mode set: off black palette register (bg3, bg2, bg1, bg0) = (1, 1, 1, 1) frc, pwm mode: 4frc, 9pwm while resetb is ? l ? or r eset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes ? l ? , any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 37 instruction description table 17 . instruction table : don ? t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read d isplay d ata 1 1 read data read data from ddram write d isplay d ata 1 0 write data write data into ddram read s tatus 0 1 busy on res mf2 mf1 mf0 ds1 ds0 read the internal status icon control register on/off 0 0 1 0 1 0 0 0 1 icon icon = 0 : icon disable (default) icon = 1 : icon enable & set the page address to 16 set p age a ddress 0 0 1 0 1 1 p3 p2 p1 p0 set page address set c olumn a ddress msb 0 0 0 0 0 1 0 y 7 y 6 y 5 set column address msb set c olumn a ddress lsb 0 0 0 0 0 0 y 4 y 3 y 2 y 1 set column address lsb set m odify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset m odify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode display o n /o ff 0 0 1 0 1 0 1 1 1 d d=0: display off d=1: display on 0 0 0 1 0 0 0 0 set i nitial d isplay l ine r egister 0 0 s6 s5 s4 s3 s2 s1 s0 2-byte i nstruction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set i nitial com0 r egister 0 0 c6 c5 c4 c3 c2 c1 c0 2-byte i nstruction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set p artial di splay d uty r atio 0 0 d 7 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to set partial display duty ratio 0 0 0 1 0 0 1 1 set n-line i nversion 0 0 n4 n3 n2 n 1 n0 2-byte i nstruction to set n -line inversion register release n-line i nversion 0 0 1 1 1 0 0 1 0 0 release n-line inversion mode reverse d isplay on/off 0 0 1 0 1 0 0 1 1 rev rev=0: normal display, rev=1: reverse display entire d isplay on/off 0 0 1 0 1 0 0 1 0 eon eon=0: normal display. eon=1: entire display on
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 38 table 1 7 . instruction table (continued) : don ? t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power c ontrol 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc-dc s tep-up 0 0 0 1 1 0 0 1 dc1 dc0 select the step-up of the internal voltage converter select r egulator r esistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 e v5 e v4 e v3 e v2 e v1 e v0 2-byte i nstruction to specify the reference voltage select lcd b ias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl s elect 0 0 1 1 0 0 shl com bi-directional selection shl=0: normal direction shl=1: reverse direction adc s elect 0 0 1 0 1 0 0 0 0 adc seg bi-directional selection adc=0: normal direction adc=1: reverse direction oscillator o n start 0 0 1 0 1 0 1 0 1 1 start the built-in oscillator set p ower s ave m ode 0 0 1 0 1 0 1 0 0 p p=0: normal mode p=1: sleep mode release p ower s ave m ode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions 1 1 1 0 1 0 0 0 set d ata d irection & display data length(ddl) d7 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to specify the number of data bytes. ( spi mode ) nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 39 table 1 7 . instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description set frc and pwm mode 0 0 1 0 0 1 0 frc pwm1 pwm0 frc(1:3frc, 0:4frc) pwm1 pwm0 0 0 9pwm 0 1 9pwm 1 0 12pwm 1 1 15pwm 0 0 1 0 0 0 1 0 0 0 set white mode and 1 st /2 nd frame, set pulse width 0 0 wb3 wb2 wb1 wb0 wa3 wa2 wa1 wa0 set white mode and 1 st /2 nd frame 0 0 1 0 0 0 1 0 0 1 set white mode and 3 rd /4 th frame, set pulse width 0 0 wd3 wd2 wd1 wd0 wc3 wc2 wc1 wc0 set white mode and 3 rd /4 th frame 0 0 1 0 0 0 1 0 1 0 set light gray mode and 1 st /2 nd frame, set pulse width 0 0 lb3 lb2 lb1 lb0 la3 la2 la1 la0 set light gray mode and 1 st /2 nd frame 0 0 1 0 0 0 1 0 1 1 set light gray mode and 3 rd /4 th frame, set pulse width 0 0 ld3 ld2 ld1 ld0 lc3 lc2 lc1 lc0 set light gray mode and 3 rd /4 th frame 0 0 1 0 0 0 1 1 0 0 set dark gray mode and 1 st /2 nd frame, set pulse width 0 0 db3 db2 d b 1 db0 da3 da2 da1 da0 set dark gray mode and 1 st /2 nd frame 0 0 1 0 0 0 1 1 0 1 set dark gray mode and 3 rd /4 th frame, set pulse width 0 0 dd3 dd2 dd1 dd0 dc3 dc2 dc1 dc0 set dark gray mode and 3 rd /4 th frame 0 0 1 0 0 0 1 1 1 0 set bl a ck mode and 1 st /2 nd frame, set pulse width 0 0 bb3 bb2 bb1 bb0 ba3 ba2 ba1 ba0 set bl a ck mode and 1 st /2 nd frame 0 0 1 0 0 0 1 1 1 1 set bl a ck mode and 3 rd /4 th frame, set pulse width 0 0 bd3 bd2 bd1 bd0 bc3 bc2 bc1 bc0 set bl a ck mode and 3 rd /4 th frame
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 40 read display data 8-bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display d ata cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8-bit data of d isplay d ata from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. during auto-increment, the column address wraps to 0 after the last column is written rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data data write set column address set page address optional status column = column + 1 no yes data write continue ? dummy data read set column address set page address optional status column = column + 1 no yes data read continue ? data read column = column + 1 figure 25 . sequence for writing display data figure 26 . sequence for reading display data
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 41 read status indicates the internal status of the s6b07 41 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy on / off res mf2 mf1 mf0 ds1 ds0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy on / off indicates display on / off status 0: display o ff , 1: display o n res et indicates the initialization is in progress by reset signal. 0: chip is active, 1: chip is being reset mf manufacturer id, mf2 mf1 mf0 = [0 0 0] ds display size id, ds1 ds0 = [1 0] icon control register on/off this instruction makes icon enable or disable. by default, icon display is disabled (icon= 0). when icon control register is set to ? 1 ? , icon display is enabled and page address is set to ? 16 ? . then user can write data for icons. it is impossible to set the page address to ? 16 ? by set page address instruction. therefore, when writing data for icons, icon control register on instruction would be used to set the page address to ? 16 ? . when icon control register is set to ? 0 ? , icon display is disabled. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 1 icon icon = 0 : icon disable (default) icon = 1 : icon enable & set the page address to 16
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 42 set page address sets the p age a ddress of display data ram from the microprocessor into the page address register. any ram data bit can be accessed when its page address and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. set page address instruction can not be used to set the page address to ? 16 ? . use icon control register on/off instruction to set the page address to ? 16 ? . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 p age 0 0 0 0 0 0 0 0 1 1 : : : : : 1 1 1 0 14 1 1 1 1 15 set column address sets the c olumn a ddress of display ram from the microprocessor into the column address register. along with the c olumn a ddress, the c olumn a ddress defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, co lumn a ddresses are automatically incre as ed. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y 7 y 6 y 5 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y 4 y 3 y 2 y 1 y 7 y 6 y 5 y 4 y 3 y 2 y 1 c olumn address [y7:y1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 43 set modify- r ead this instruction stops the automatic increment of the column address by the r ead d isplay d ata instruction, but the column address is still increased by the w rite d isplay d ata instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the r eset modify- r ead instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify-read this instruction cancels the modify- r ead mode, and makes the column address return to its initial value just before the s et modify - read instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify-read reset modify-read set page address data process no yes change completed? set column address (n) dummy read data read data write return column address (n) figure 27 . sequence for cursor display
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 44 display on / off turns the display on or off . this command has priority over entire display on/off and reverse display on/off. commands are accepted while the display is off, but the visual state of the display does not change. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d on d on = 1: display on d on = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2-byte instruction. the ram display data is displayed at the top of row(com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s 6 s 5 s 4 s 3 s 2 s 1 s 0 s 6 s 5 s 4 s 3 s 2 s 1 s 0 line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 3 : : : : : : : : 1 1 1 1 1 0 0 124 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i initial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 28 . the sequence for setting the initial display line
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 45 set initial com0 register sets the initial row (com) of the lcd panel using the 2-byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 0 0 0 0 0 1 1 com3 : : : : : : : : 1 1 1 1 1 0 0 com 124 1 1 1 1 1 0 1 com 125 1 1 1 1 1 1 0 com 126 1 1 1 1 1 1 1 com 127 2 nd i nstruction ( i nitial com0 s etting) setting i nitial com0 e nd 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 29 . sequence for setting the initial com0
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 46 set partial display duty ratio sets the duty ratio within range of 16 to 128 (icon disabled) or 17 to 129 (icon enabled) to realize partial display by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 d 7 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio (icon disabled) selected partial duty ratio (icon enabled) 0 0 0 0 0 0 0 0 : : : : : : : : 0 0 0 0 1 1 1 1 no operation no operation 0 0 0 1 0 0 0 0 1/ 16 1/ 17 0 0 0 1 0 0 0 1 1/1 7 1/1 8 : : : : : : : : : : 0 1 1 1 1 1 1 1 1/ 127 1/ 128 1 0 0 0 0 0 0 0 1/ 128 1/ 129 1 0 0 0 0 0 0 1 : : : : : : : : 1 1 1 1 1 1 1 1 no operation no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 30 . sequence for setting partial display
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 47 set n-line inversion register sets the inverted line number within range of 3 to 3 3 to improve the display quality by controlling the phase of the internal lcd ac signal (m) by using the 2-byte instruction. the dc-bias problem could be occurred if k is even number. so, we recommend customers to set k to be odd number. k : d/n d : the number of display duty ratio (d is selectable by customers) n : n for n-line inversion (n is selectable by customers). the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 n4 n3 n2 n1 n0 n4 n3 n2 n1 n0 selected n-line inversion 0 0 0 0 0 0-line inversion (frame inversion) 0 0 0 0 1 3-line inversion 0 0 0 1 0 4 -line inversion 0 0 0 1 1 5 -line inversion : : : : : : 1 1 1 0 1 3 1 -line inversion 1 1 1 1 0 3 2 -line inversion 1 1 1 1 1 3 3 -line inversion 2 nd i nstruction ( n - l ine i nversion s etting) setting n - l ine i nversion e nd 1 st i nstruction ( m ode s etting) setting n - l ine i nversion s tart figure 31 . sequence for n-line inversion release n-line inversion returns to the frame inversion condition from the n-line inversion condition. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 1 0 0
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 48 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ddram data = ? 00 ? ? white ddram data = ? 0 1 ? ? light gray ddram data = ? 1 0 ? ? dark gray ddram data = ? 11 ? ? dark 0 (normal) white ( ? 00 ? ) light gray ( ? 01 ? ) dark gray ( ? 10 ? ) dark ( ? 11 ? ) 1 (reverse) dark ( ? 11 ? ) dark gray ( ? 10 ? ) light gray ( ? 01 ? ) white ( ? 00 ? ) entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the r everse display o n / o ff instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon e on ddram data = ? 00 ? ? white ddram data = ? 0 1 ? ? light gray ddram data = ? 1 0 ? ? dark gray ddram data = ? 11 ? ? dark 0 (normal) white ( ? 00 ? ) light gray ( ? 01 ? ) dark gray ( ? 10 ? ) dark ( ? 11 ? ) 1 ( entire ) dark ( ? 11 ? ) dark ( ? 11 ? ) dark ( ? 11 ? ) dark ( ? 11 ? ) power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 49 select dc-dc step-up selects one of 4 dc-dc step-up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc-dc converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit 1 1 6 times boosting circuit select regulator resistor selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the t able 1 4 . rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 1+ ( rb / ra ) 0 0 0 2.3 0 0 1 3.0 0 1 0 3.7 0 1 1 4.4 1 0 0 5.1 1 0 1 5.8 1 1 0 6.5 1 1 1 7.2
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 50 set electronic volume register consist of 2-byte instruction s the 1 st instruction set reference voltage mode , the 2 nd one updates the contents of reference vol tage register. after second instruction, reference voltage m ode is released. the 1 st instruction : set reference voltage select m ode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction : set reference voltage r egister rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 e v5 e v4 e v3 e v2 e v1 e v0 e v5 e v4 e v3 e v2 e v1 e v0 reference voltage p arameter ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd instruction for register setting setting r eference v oltage end 1 st instruction for mode setting setting r eference v oltage start figure 32 . sequence for setting the electronic volume
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 51 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 lcd bias 0 0 0 1/ 5 0 0 1 1/ 6 0 1 0 1/ 7 0 1 1 1/8 1 0 0 1/ 9 1 0 1 1/ 10 1 1 0 1/11 1 1 1 1/ 12 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl : don ? t care shl = 0: normal direction (com 0 ? com 127 ) shl = 1: reverse direction (com 127 ? com 0 ) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins c ould be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg 0 ? seg 127 ) adc = 1: reverse direction (seg 127 ? seg 0 )
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 52 oscillator on start this instruction enables the built-in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 power save the s6b07 41 enters the power save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: normal mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 sleep mode oscillator circuits: off lcd power supply circuits: off all com / seg output level: vss consumption current < 2 ua set power save mode (sleep mode) release power save mode (sleep mode) figure 33 . power save routine
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 53 reset this instruction r esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply , which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0 set data direction & display data length (3-pin spi mode) consists of 2 bytes instruction. this command is used in 3-pin spi mode only (ps0 = ? l ? and ps1 = ? l ? ) . it will be two continuous commands, the first byte control the data direction (write mode only) and inform the lcd driver the second byte will be number of data bytes will be write. when rs is not used, the display data length instruction is used to indicate that a specified number of display data bytes are to be transmitted. the next byte after the display data string is handled as command data. the 1 st instruction: set data direction (only write mode) rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x 1 1 1 0 1 0 0 0 the 2 nd instruction: set display data length (ddl) register rs rw db7 db6 db5 db4 db3 db2 db1 db0 x x d7 d6 d5 d4 d3 d2 d1 d 0 d7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 display data length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 nop no operation rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 54 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1 s et pwm & frc mode selects 3/4 frc and 9 / 12 / 15 pwm rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 0 frc pwm1 pwm0 frc pwm1 pwm0 status of pwm & frc 0 1 4frc 3frc 0 0 1 1 0 1 0 1 9pwm 9pwm 12pwm 15pwm
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 55 set gray scale mode & register consists of 2 bytes instruction. the first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction. - set gray scale mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 1 gm2 gm1 gm0 gm2 gm1 gm0 description 0 0 0 in case of setting white mode and 1 st / 2 nd frame 0 0 1 in case of setting white mode and 3 rd / 4 th frame 0 1 0 in case of setting light gray mode and 1 st / 2 nd frame 0 1 1 in case of setting light gray mode and 3 rd / 4 th frame 1 0 0 in case of setting dark gray mode and 1 st / 2 nd frame 1 0 1 in case of setting dark gray mode and 3 rd / 4 th frame 1 1 0 in case of setting black mode and 1 st / 2 nd frame 1 1 1 in case of setting black mode and 3 rd / 4 th frame - set gray scale register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 gb3 gb2 gb1 gb0 ga3 ga2 ga1 ga0 0 0 gd3 gd2 gd1 gd0 gc3 gc2 gc1 gc0 ga3, gb3, gc3, gd3 ga2, gb2, gc2, gd2 ga1, gb1, gc1, gd1 ga0, gb0, gc0, gd0 pulse w idth (9pwm) pulse w idth (12pwm) pulse w idth (15pwm) 0 0 0 0 0/9 0/12 0/15 0 0 0 1 1/9 1/12 1/15 : : : : : : : 1 0 0 1 9/9 9/12 9/15 1 0 1 0 0/9 10/12 10/15 1 0 1 1 0/9 11/12 11/15 1 1 0 0 0/9 12/12 12/15 1 1 0 1 0/9 0/12 13/15 1 1 1 0 0/9 0/12 14/15 1 1 1 1 0/9 0/12 15/15 * ga3=wa3,la3,da3,ba3 ga2=wa2,la2,da2,ba2 ga1=wa1,la1,da1,ba1 ga0=wa0,la0,da0,ba0 gb3=wb3,lb3,db3,bb3 ga2=wb2,lb2,db2,bb2 ga1=wb1,lb1,db1,bb1 ga0=wb0,lb0,db0,bb0 gc3=wc3,lc3,dc3,bc3 ga2=wc2,lc2,dc2,bc2 ga1=wc1,lc1,dc1,bc1 ga0=wc0,lc0,dc0,bc0 gd3=wd3,ld3,dd3,bd3 ga2=wd2,ld2,dd2,bd2 ga1=wd1,ld1,dd1,bd1 ga0=wd0,ld0,dd0,bd0
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 56 referential instruction set - up flow: initializing with the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power resetb pin = "h" user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of initialization [ gray-scale select] figure 34 . initializing with the b uilt-in p ower s upply c ircuits
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 57 referential instruction set - up flow: initializing with out the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save [gray-scale select] figure 35 . initializing without the b uilt-in p ower s upply c ircuits
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 58 referential instruction set-up flow: data displaying end of initialization write display data by instruction [display data write] turn display on / off instruction [display on / off] end of data display display data ram addressing by instruction [initial display line] [set page address] [set column address] figure 36 . data d isplaying r eferential instruction set - up flow: power off optional status power off (vdd-vss) end of power off set power save by instruction figure 37. power o ff
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 59 referential instruction set - up flow: partial duty changing start of partial changing set display off by internal [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set s leep mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels [gray-scale select] figure 38 . partial duty changing
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 60 specifications absolute maximum ratings table 18 . absolute maximum ratings (v ss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 7.0 v v0, vout - 0.3 ~ + 17 .0 v supply voltage range v1, v2, v3, v4 - 0.3 ~ v0 + 0.3 v external reference voltage vext +0.3 ~ v dd input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 40 ~ + 85 c storage temperature range t str - 55 ~ + 125 c notes: 1. v dd, v0, vout, v1 to v4 and vext are based on v ss = 0v. 2. voltages v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. (vlcd = v0 ? vss) 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 61 dc characteristics table 19. dc characteristics (v ss = 0v, v dd = 1 . 8 to 3.3 v, ta = -40 to 85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 1 . 8 - 3.3 v vdd ( *1 ) operating voltage (2) v0 4.0 - 1 5 .0 v v0 ( *2 ) high v ih 0. 8 v dd - v dd input voltage low v il v ss - 0. 2 v dd v ( *3 ) high v oh i oh = -0.5ma 0. 8 v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0. 2 v dd v ( *4 ) input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a ( * 3) output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a ( * 5) lcd driver on resistance r on ta = 25 c, v0 = 8v - 2.0 3.0 k w segn comn ( * 6) operating frequency f fr ta = 25 c 1/128 duty, 9 pwm rext = 620k w ( * 11) 70 85 100 hz ( *7 ) (*11) 3 1.8 - 5.0 4 1.8 - 3.75 5 1.8 - 3.0 voltage converter input voltage v ci 6 1.8 - 2.5 v v ci voltage converter output voltage v out x3 / 4 / 5 / 6 voltage conversion (no-load ) 95 99 - % vout voltage regulator operating voltage v out 5.4 - 1 5 .0 v vout voltage follower operating voltage v0 4.0 - 1 5 .0 v v0 ( * 8) reference voltage v ref ta = 25 c 2.04 2.10 2.16 v ( * 9)
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 62 dynamic current consumption when the internal power supply is on table 20 . dynamic current 2 (internal power) (v dd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 2 .0v, x 5 boosting, duty = 1/ 128 , normal mode (display off) - 100 150 m a ( *10 ) dynamic current consumption i dd v0 - vss = 1 2 .0v, x 5 boosting, duty = 1/ 128 , normal mode (display on , checker pattern) - 200 300 m a ( * 10) current consumption during power save mode table 21. power save mode current (v dd = 3 . 0 v, ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during sleep - - 2 m a (*10)
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 63 table 22 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on-chip oscillator circuit is used f fr x n f fr x pwm x 2 x n ( f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 16 to 129 ) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . csb, rs, db0 to db7, e_rd, rw_wr, resetb, ps1 , ps 0 , intrs and ref *4 . db0 to db7 *5 . applies when the db0 to db7 pins are in high impedance. *6 . resistance value when -0.1[ ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ ma] ( d v : voltage change when -0.1[ ma] is applied in the on status.) *7 . see table 23 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. *9 . on-chip reference voltage source of the voltage regulator circuit to adjust v0. *10 . applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on. the current flowing through voltage regulation resistors( rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc. other conditions are 1/12 bias, 3 frc, 9 pwm, frame inversion, frame freq. = 85hz, bl=(9,9,9,0), dg=(6,6,6,0), lg=(3,3,3,0), wh=(0,0,0,0). *1 1. applies when pwm method is used. when both pwm and frc method are used, frame frequency should be increased up to more than 130hz. so, oscillator resistor value between osc1 and vdd pin should be reduced.
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 64 ac characteristics read / write characteristics (8080-series mpu) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwl t cy80 t ah80 t as80 db0 to db7 ( write ) db0 to db7 ( read ) /rd, /wr csb rs t pwh figure 39. read / write c haracteristics (8080-series mpu) (v dd = 1 . 8 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time for write system cycle time for read t cy80 t cy80 150 330 - ns pulse width low pulse width high / wr / rd t pwl t pwh 60 60 - - ns data setup time data hold time t ds80 t dh80 40 10 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf 15 10 - 5 0 ns (v dd = 2.7 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time for write system cycle time for read t cy80 t cy80 100 166 - ns pulse width low pulse width high / wr / rd t pwl t pwh 40 40 - - ns data setup time data hold time t ds80 t dh80 30 5 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf 15 10 - 5 0 ns note: *1. the input signal rise time and fall time ( tr, tf) is specified at 15 ns or less. ( tr + tf) < (t cy80 - t pwlw - t pwhw ) for write, ( tr + tf) < (t cy80 - t pwlr - t pwhr ) for read
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 65 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewh t ah68 db0 to db7 ( write ) db0 to db7 ( read ) e rs, r/w t ewl 0. 9 v dd 0. 1 v dd t ew l t cy68 t as68 csb t ew h figure 40. read / write characteristics (6800-series microprocessor) (v dd = 1 . 8 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time for write system cycle time for read t cy68 t cy68 150 330 - ns enable width high enable width low e_rd (e) t ewh t ewl 60 60 - - ns data setup time data hold time t ds68 t dh68 40 10 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf 15 10 - 5 0 ns (v dd = 2 . 7 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time for write system cycle time for read t cy68 t cy68 100 166 - ns enable width high enable width low e_rd (e) t ewh t ewl 40 40 - - ns data setup time data hold time t ds68 t dh68 30 5 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf 15 10 - 5 0 ns note: *1. the input signal rise time and fall time ( tr, tf) is specified at 15 ns or less. ( tr + tf) < (t cy 68 - t ewhw - t ewlw ) for write, ( tr + tf) < (t cy 68 - t ewhr - t ewlr ) for read
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 66 serial interface characteristics db7 (sid) db6 (sclk) rs csb t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 41. serial interface characteristics (v dd = 1 . 8 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cy s t w hs t w ls 111 60 60 - - - ns address setup time address hold time rs t ass t ahs 6 0 6 0 - - ns data setup time data hold time db7 (sid) t dss t dhs 6 0 6 0 - - ns csb setup time csb hold time csb t css t chs 6 0 1/2 * t cy s - - ns (v dd = 2 . 7 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) t cy s t w hs t w ls 58.8 30 30 - - - ns address setup time address hold time rs t ass t ahs 3 0 3 0 - - ns data setup time data hold time db7 (sid) t dss t dhs 3 0 3 0 - - ns csb setup time csb hold time csb t css t chs 3 0 1/2 * t cy s - - ns note: *1. the input signal rise time and fall time ( tr, tf) is specified at 15 ns or less.
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 67 reset input timing resetb internal status t rw t r reset complete during reset figure 42. reset input timing (v dd = 1 . 8 ~ 3 . 3 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 1 000 - ns reset time - t r - 1 000 ns
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 68 reference applications microprocessor interface in case of interfacing with 6800-series (ps 0 = ? h ? , ps1 = ? h ? ) db0 to db7 resetb v dd v dd rw e rs cs b 6800-series mpu cs b rs e_rd rw_wr db0 to db7 resetb ps0 ps 1 s6b0 7 41 figure 43. i nterfacing with 6800-series (ps 0 = ? h ? , c68 = ? h ? ) in case of interfacing with 8080-series (ps 0 = ? h ? , ps1 = ? l ? ) db0 to db7 resetb v ss v dd /wr /rd rs cs b 8080-series mpu cs b rs e_rd rw_wr db0 to db7 resetb ps0 ps 1 s6b 07 41 figure 44. i nterfacing with 8080-series (ps 0 = ? h ? , c68 = ? l ? )
s6b 07 41 128 seg / 129 com driver & controller for stn lcd 69 in case of 4- p in spi mode (ps0 = "l" , ps1 = " h " ) open resetb v ss sclk sid rs cs b mpu cs b rs db7(sid) db6(sclk) resetb db0 to db5 ps 0 ps 1 s6b 07 41 v dd figure 45. s erial interface (ps 0 = ? l ? , ps 1 = ? h ? ) in case of 3- p in spi mode (ps0 = "l" , ps1 = "l" ) open resetb v ss sclk sid cs b mpu cs b db7(sid) db6(sclk) resetb db0 to db5 ps 0 ps 1 s6b0 7 41 v ss figure 46. s erial interface (ps 0 = ? l ? , ps 1 = ? l ? )
128 seg / 1 29 com driver & controller for stn lcd s6b 07 41 70 connections between s6b07 4 1 and lcd panel single chip configuration (1/ 129 duty configurations) com 63 : com 0 coms coms com 127 : com 64 seg 127 ........... seg 0 s 6b 07 41 ( bottom view) com 63 : com 0 coms coms com 127 : com 64 seg 0 ............ seg 127 s 6b 07 41 ( top view) ? a x a ? a x a 129 1 28 pixels ? a x a ? a x a 129 1 28 pixels figure 47 . shl = 0, adc = 1 figure 48 . shl = 0, adc = 0 ? a x a ? a x a coms com 0 : co m63 co m127 : com 64 coms se g127 ........... se g0 s 6b 07 41 ( top view) ? a x a ? a x a 129 1 28 pixels com 64 : com 127 coms coms com 0 : com 63 seg 0 ........... seg 127 s 6b 07 41 ( bottom view) 129 1 28 pixels figure 49 . shl = 1, adc = 0 figure 50 . shl = 1, adc = 1

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